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INTEGRATED CIRCUITS
87C524/87C528 80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
Product specification
Replaces data sheets 87C524 of 1998 May 01 and 87C528 of 1998 May 01
1999 Jul 23
IC28 Data Handbook
Philips Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
FEATURES
* 80C51 instruction set
- 512 x 8 RAM - Memory addressing capability 64k ROM and 64k RAM - Three 16-bit counter/timers - On-chip watchdog timer with oscillator - Full duplex UART - I2C serial interface
DESCRIPTION
The 87C528 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C528 has the same instruction set as the 80C51. Three versions of the derivative exist:
* Power control modes:
- Idle mode - Power-down mode - Warm start from power-down
* 83C528--32k bytes ROM * 83C524--16k bytes ROM * 80C528--ROMless version of the 83C528 * 87C528--32k bytes EPROM * 83C524--16k bytes EPROM
* CMOS and TTL compatible * Extended temperature ranges * EPROM code protection * OTP package available * 16 MHz speed at VCC = 5 V
This device provides architectural enhancements that make it applicable in a variety of applications in consumer, telecom and general control systems, especially in those systems which need large ROM and RAM capacity on-chip. The 87C528 contains a 32k x 8 EPROM and the 87C524 contains a 16k x 8 EPROM. Both devices have a 512 x 8 RAM, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the timer 2 of the 80C52), a watchdog timer with a separate oscillator, a multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and I2C-bus), and on-chip oscillator and timing circuits. In addition, the 87C524/87C528 has two software selectable modes of power reduction--idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
ORDERING INFORMATION
EPROM P87C528EBP N P87C528EBA A P87C528EBB B P87C528EFP N P87C528EFB B P87C524EBA A TEMPERATURE oC RANGE AND PACKAGE 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Dual In-line Package -40 to +85, Plastic Quad Flat Pack 0 to +70, Plastic Leaded Chip Carrier FREQ (MHz) 16 16 16 16 16 16 16 Drawing Number SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT307-2 SOT187-2 SOT307-2
P87C524EBB B 0 to +70, Plastic Quad Flat Pack NOTE: 1. For ROM & ROMless devices, see data sheet P8X524/528.
1999 Jul 23
2
853-1687 22041
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
BLOCK DIAGRAM
FREQUENCY REFERENCE XTAL2 XTAL1
COUNTERS T0 T1 T2 T2EX RST
RAM OSCILLATOR AND TIMING PROGRAM MEMORY (32K x 8 EPROM) DATA MEMORY (256 x 8)
AUX-RAM DATA MEMORY (256 x 8) TWO 16-BIT TIMER/EVENT COUNTERS 16-BIT TIMER/ EVENT COUNTER WATCHDOG TIMER
CPU
INTERNAL INTERRUPTS
64K-BYTE BUS EXPANSION CONTROL
PROGRAMMABLE I/O
PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT
BIT-LEVEL I2C INTERFACE
INT0 INT1 EXTERNAL INTERRUPTS
CONTROL
PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS
SERIAL IN
SERIAL OUT
SDA
SCL
SHARED WITH PORT 3
SU00166
LOGIC SYMBOL
VDD XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
XTAL2 T2 T2EX RST EA PSEN SECONDARY FUNCTIONS ALE RxD TxD INT0 INT1 T0 T1 WR RD PORT 1
SCL SDA
PORT 3
PORT 2
ADDRESS BUS
SU00165
1999 Jul 23
3
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
PIN CONFIGURATIONS
T2/P1.0 1 T2EX/P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 SCL/P1.6 7 SDA/P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DUAL IN-LINE PACKAGE 40 VDD
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 17 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD 18 28 29 LCC 7 39 1 40
SU00162
* NO INTERNAL CONNECTIONS
SU00163A
1999 Jul 23
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Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
1
33
QFP
11
23
12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
22 Function P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4
* NO INTERNAL CONNECTIONS
SU00164
1999 Jul 23
5
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
PIN DESCRIPTIONS
PIN NO. MNEMONIC VSS VDD P0.0-0.7 DIP 20 40 39-32 LCC 22 44 43-36 QFP 16 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: circuit ground potential. Power Supply: +5 V power supply pin during normal operation, Idle mode and Power-down mode. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which have open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 can sink/source one TTL (4 LSTTL) inputs. Port 1 receives the low-order address byte during program memory verification. Port 1 also serves alternate functions for timer 2: T2 (P1.0): Timer/counter 2 external count input (following edge triggered). T2EX (P1.1): Timer/counter 2 trigger input. SCL (P1.6): I2C serial port clock line. SDA (P1.7): I2C serial port data line. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. After a watchdog timer overflow, this pin is pulled high while the internal reset signal is active. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low during RESET to enable the device to fetch code from external program memory locations 0000H to 7FFFH. If EA is held high during RESET, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. EA is don't care after RESET. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
P1.0-P1.7
1-8
2-9
40-44 1-3
I/O
1 2 7 8 P2.0-P2.7 21-28
2 3 8 9 24-31
40 41 2 3 18-25
I I I/O I/O I/O
P3.0-P3.7
10-17
11, 13-19
5, 7-13
I/O
10 11 12 13 14 15 16 17 RST 9
11 13 14 15 16 17 18 19 10
5 7 8 9 10 11 12 13 4
I O I I I I O O I/O
ALE
30
33
27
I/O
PSEN
29
32
26
O
EA
31
35
29
I
XTAL1 XTAL2
19 18
21 20
15 14
I O
1999 Jul 23
6
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Table 1.
SYMBOL ACC* B* DPTR: DPH DPL IE*# IP*#
8XC524/8XC528 Special Function Registers
DESCRIPTION Accumulator B register Data pointer (2 bytes): Data pointer high Data pointer low Interrupt enable Interrupt priority DIRECT ADDRESS E0H F0H 83H 82H AF A8H B8H EA BF - 87 AE ES1 BE PS1 86 AD6 96 SEL A6 A14 B6 WR - D6 AC AD ET2 BD PT2 85 AD5 95 - A5 A13 B5 T1 - D5 F0 AC ES0 BC PS0 84 AD4 94 - A4 A12 B4 T0 - D4 RS1 AB ET1 BB PT1 83 AD3 93 - A3 A11 B3 INT1 GF1 D3 RS0 AA EX1 BA PX1 82 AD2 92 - A2 A10 B2 INT0 GF0 D2 OV A9 ET0 B9 PT0 81 AD1 91 T2EX A1 A9 B1 TxD PD D1 F1 A8 EX0 B8 PX0 80 AD0 90 T2 A0 A8 B0 RxD IDL D0 P 00H 00H 00H xxxxxxxxB 9F 9E SM1 0 X X DE SCI SC0 8E TR1 CE EXF2 9D SM2 0 X X DD CLH CLH 8D TF0 CD RCLK 9C REN 0 X X DC BB X 8C TR0 CC TCLK 9B TB8 0 X X DB RBF X 8B IE1 CB EXEN2 9A RB8 0 X X DA WBF X 8A IT1 CA TR2 99 TI 0 X X D9 STR STR 89 IE0 C9 C/T2 98 RI 0 X X D8 ENS ENS 88 IT0 C8
CP/RL2
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0
RESET VALUE 00H 00H 00H 00H 00H x0000000B
P0*
Port 0
80H
AD7 97
FFH
P1*
Port 1
90H
SDA A7
FFH
P2*
Port 2
A0H
A15 B7
FFH
P3* PCON
Port 3 Power control
B0H 87H
RD SMOD D7
FFH 0xxx0000B
PSW* RCAP2H# RCAP2L# SBUF SCON* S1BIT# S1INT# S1SCS*# SP TCON* T2CON*# TH0 TH1 TH2# TL0 TL1 TL2# T3# TMOD WDCON#
Program status word Capture high Capture low Serial data buffer Serial controller Serial I2C data
D0H CBH CAH 99H 98H D9H/RD WR DAH D8H/RD WR 81H
CY
SM0 SDI SD0 INT DF SDI SD0 8F
00H x0000000B 0xxxxxxxB 0xxxxxxxB xxxx0000B 00xxxx00B 07H
Serial I2C interrupt Serial I2C control Stack pointer Timer control Timer 2 control Timer high 0 Timer high 1 Timer high 2 Timer low 0 Timer low 1 Timer low 2 Watchdog timer Timer mode Watchdog control
88H C8H 8CH 8DH CDH 8AH 8BH CCH FFH 89H A5H
TF1 CF TF2
00H 00H 00H 00H 00H 00H 00H 00H 00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H A5H
* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1999 Jul 23 7
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Table 2. Internal and External Program Memory Access with Security Bit Set
INSTRUCTION MOVC in internal program memory MOVC in external program memory ACCESS TO INTERNAL PROGRAM MEMORY YES NO ACCESS TO EXTERNAL PROGRAM MEMORY YES YES the watchdog timer, the user program has to reload the watchdog timer within periods that are shorter than the programmed watchdog timer internal. This time interval is determined by an 8-bit value that has to be loaded in register T3 while at the same time the prescaler is cleared by hardware. Watchdog timer interval = [256 * (T3)] 2048 on * chip oscillator frequency
INTERNAL DATA MEMORY
The internal data memory is divided into three physically separated segments: 256 bytes of RAM, 256 bytes of AUX-RAM, and a 128 bytes special function area. These can be addressed each in a different way. - RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. - RAM 128 to 255 can only be addressed indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank. - AUX-RAM 0 to 255 is indirectly addressed in the same way as external data memory with the MOVX instructions. Address pointers are R0, R1 of the selected register bank and DPTR. An access to AUX-RAM 0 to 255 will not affect ports P0, P2, P3.6 and P3.7. An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 8051 structure, so with P0 and P2 as data/address bus and P3.6 and P3.7 as write and read timing signals. Note that these external data memory cannot be accessed with R0 and R1 as address pointer.
BIT-LEVEL I2C INTERFACE
This bit-level serial I/O interface supports the I2C-bus. P1.6/SCL and P1.7/SDA are the serial I/O pins. These two pins meet the I2C specification concerning the input levels and output drive capability. Consequently, these pins have an open drain output configuration. All the four modes of the I2C-bus are supported: - master transmitter - master receiver - slave transmitter - slave receiver The advantages of the bit-level I2C hardware compared with a full software I2C implementation are: - the hardware can generate the SCL pulse - Testing a single bit (RBF respectively, WBF) is sufficient as a check for error free transmission. The bit-level I2C hardware operates on serial bit level and performs the following functions: - filtering the incoming serial data and clock signals - recognizing the START condition - generating a serial interrupt request SI after reception of a START condition and the first falling edge of the serial clock - recognizing the STOP condition - recognizing a serial clock pulse on the SCL line - latching a serial bit on the SDA line (SDI) - stretching the SCL LOW period of the serial clock to suspend the transfer of the next serial data bit - setting Read Bit Finished (RBF) when the SCL clock pulse has finished and Write Bit Finished (WBF) if there is no arbitration loss detected (i.e., SDA = 0 while SDO = 1) - setting a serial clock Low-to-High detected (CLH) flag - setting a Bus Busy (BB) flag on a START condition and clearing this flag on a STOP condition - releasing the SCL line and clearing the CLH, RBF and WBF flags to resume transfer of the next serial data bit - generating an automatic clock if the single bit data register S1BIT is used in master mode. The following functions must be done in software: - handling the I2C START interrupts - converting serial to parallel data when receiving - converting parallel to serial data when transmitting - comparing the received slave address with its own - interpreting the acknowledge information - guarding the I2C status if RBF or WBF = 0.
TIMER 2
Timer 2 is functionally equal to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter. These 16 bits are formed by two special function registers TL2 and TH2. Another pair of special function register RCAP2L and RCAP2H form a 16-bit capture register or a 16-bit reload register. Like Timer 0 and 1, it can operate either as a timer or as an event counter. This is selected by bit C/T2N in the special function register T2CON. It has three operating modes: capture, autoload, and baud rate generator mode which are selected by bits in T2CON.
WATCHDOG TIMER T3
The watchdog timer consists of an 11-bit prescaler and an 8-bit timer formed by special function register T3. The prescaler is incremented by an on-chip oscillator with a fixed frequency of 1MHz. The maximum tolerance on this frequency is -50% and +100%. The 8-bit timer increments every 2048 cycles of the on-chip oscillator. When a timer overflow occurs, the microcontroller is reset and a reset output pulse of 16 x 2048 cycles of the on-chip oscillator is generated at pin RST. The internal RESET signal is not inhibited when the external RST pin is kept low by, for example, an external reset circuit. The RESET signal drives port 1, 2, 3 into the high state and port 0 into the high impedance state. The watchdog timer is controlled by one special function register WDCON with the direct address location A5H. WDCON can be read and written by software. A value of A5H in WDCON halts the on-chip oscillator and clears both the prescaler and timer T3. After the RESET signal, WDCON contains A5H. Every value other than A5H in WDCON enables the watchdog timer. When the watchdog timer is enabled, it runs independently of the XTAL-clock. Timer T3 can be read on the fly. Timer T3 can only be written if WDCON contains the value 5AH. A successful write operation to T3 will clear the prescaler and WDCON, leaving the watchdog enabled and preventing inadvertent changes of T3. To prevent an overflow of
1999 Jul 23
8
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Additionally, if acting as master: - generating START and STOP conditions - handling bus arbitration - generating serial clock pulses if S1BIT is not used. Three SFRs control the bit-level I2C interface: S1INT, S1BIT and S1SCS.
IE: Interrupt Enable Register
This register is located at address A8H. Refer to Table 3. IE SFR (A8H) 7 EA 6 ES1 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
IP: Interrupt Priority Register INTERRUPT SYSTEM
The interrupt structure of the 8XC528 is the same as that used in the 80C51, but includes two additional interrupt sources: one for the third timer/counter, T2, and one for the I2C interface. The interrupt enable and interrupt priority registers are IE and IP. This register is located at address B8H. Refer to Table 4. IP SFR (B8H) 7 - 6 PS1 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
Table 3. Description of IE Bits
MNEMONIC EA BIT IE.7 FUNCTION General enable/disable control: 0 = NO interrupt is enabled. 1 = ANY individually enabled interrupt will be accepted. Enable bit-level I2C I/O interrupt Enable Timer 2 interrupt Enable Serial Port interrupt Enable Timer 1 interrupt Enable External interrupt 1 Enable Timer 0 interrupt Enable External interrupt 0
ES1 ET2 ES ET1 EX1 ET0 EX0
IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
Table 4. Description of IP Bits
MNEMONIC - PS1 PT2 PS PT1 PX1 PT0 PX0 BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 FUNCTION Reserved. Bit-level I2C interrupt priority level Timer 2 interrupt priority level Serial Port interrupt priority level Timer 1 interrupt priority level External Interrupt 1 priority level Timer 0 interrupt priority level External Interrupt 0 priority level
The interrupt vector locations and the interrupt priorities are: Source Vector 0003H 002BH 0053H 000BH 0013H 001BH 0023H Priority within Level Address IE0 TF2+EXF2 SI (I2C) TF0 IE1 TF1 RI+TI Highest
Lowest
1999 Jul 23
9
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. The power-down mode can be terminated by a RESET in the same way as in the 80C51 or in addition by one of two external interrupts, INT0 or INT1. A termination with an external interrupt does not affect the internal data memory and does not affect the special function registers. This makes it possible to exit power-down without changing the port output levels. To terminate the power-down mode with an external interrupt INT0 or INT1 must be switched to level-sensitive and must be enabled. The external interrupt input signal INT0 and INT1 must be kept low until the oscillator has restarted and stabilized. An instruction following the instruction that puts the device in the power-down mode will be executed. A reset generated by the watchdog timer terminates the power-down mode in the same way as an external RESET, and only the contents of the on-chip RAM are preserved. The control bits for the reduced power modes are in the special function register PCON.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-up, the voltage on VDD and RST must come up at the same time for a proper start-up.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
DESIGN CONSIDERATIONS
At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. Table 5 shows the state of I/O ports during low current operating modes.
Table 5. External Pin Status During Idle and Power-Down Modes
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on any other pin to VSS Input, output current on any two pins Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70, or -40 to +85 -65 to +150 -0.5 to VDD +0.5 10 1.0 UNIT C C V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1999 Jul 23
10
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C (VDD = 5 V 10%), -40C to +85C (VDD = 5 V 10%), VSS=0 V TEST SYMBOL VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOL2 VOH VOH1 IIL ITL IIL1 IIL2 ICC PARAMETER Input low voltage, except EA, P1.6/SCL, P1.7/SDA Input low voltage to EA Input low voltage to P1.6/SCL, P1.7/SDA5 Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA Input high voltage, XTAL1, RST Input high voltage, P1.6/SCL, P1.7/SDA5 Output low voltage, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA1 Output low voltage, port 0, ALE, PSEN1 Output low voltage, P1.6/SCL, P1.7/SDA Output high voltage, ports 1, 2, 3 Output high voltage, Port 0 in external bus mode, ALE, PSEN, RST Logical 0 input current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA Input leakage current, port 0 Input leakage current, P1.6/SCL, P1.7/SDA Power supply current: Active mode @ 16 MHz Idle mode @ 16 MHz Power down mode RRST CIO Internal reset pull-down resistor Pin Capacitance 50 0oC to 70oC -40oC to +85oC 0oC to 70oC -40oC to +85oC 0C to 70C -40C to +85C 0C to 70C -40C to +85C IOL = 1.6 mA1 0C to 70C -40C to +85C 0C to 70C -40C to +85C PART TYPE 0C to 70C -40C to +85C 0C to 70C -40C to +85C CONDITIONS MIN -0.5 -0.5 0 0 -0.5 0.2VCC+0.9 0.2VCC+1.0 0.7VCC 0.7VCC+0.1 3.0 LIMITS MAX 0.2VCC-0.1 0.2VCC-0.15 0.2VCC-0.3 0.2VCC-0.35 0.3 V VCC+0.5 VCC+0.5 VCC+0.5 VCC+0.5 6.0 0.45 0.45 0.4 2.4 0.75VCC 2.4 0.75VCC -50 -75 -650 -750 10 10 UNIT V V V V V V V V V V V V V V V V V A A A A A A A
IOL = 3.2 mA1 IOL = 3.0 mA1 IOH = -60 A IOH = -25 A IOH = -800 A IOH = -300 A VIN = 0.45 V See Note 3 VIN = VIL or VIH 0 V25 35 5 6 50 300 10
mA mA A k pF
NOTES: 1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port and port 2 pins when these pins make 1-to-0 transactions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 10 mA per port pin, port 0 total (all bits) 26 mA, ports 1, 2, and total each (all bits) 15 mA. 2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 3. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 4. See Figures 10 through 13 for ICC test conditions. 5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
1999 Jul 23
11
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
AC ELECTRICAL CHARACTERISTICS1, 2
16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDZ tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV 4 4 4 4 4 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid 750 492 8 0 492 12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133 ns ns ns ns ns 6 6 6 6 High time Low time Rise time Fall time 20 20 20 20 20 20 20 20 ns ns ns ns 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high 23 138 120 3 13 0 103 tCLCL-40 0 55 350 398 238 3tCLCL-50 4tCLCL-130 tCLCL-60 tCLCL-50 0 tCLCL+40 275 275 148 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 1 1 1 1 1 1 1 1 1 1 1 1 PARAMETER Oscillator frequency: 87C528 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 38 208 10 23 143 83 0 tCLCL-25 5tCLCL-105 10 Speed Versions P878C528EXX 85 8 28 150 tCLCL-40 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-55 tCLCL-35 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
1999 Jul 23
12
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
AC ELECTRICAL CHARACTERISTICS - I2C INTERFACE
SYMBOL PARAMETER INPUT OUTPUT I2C SPECIFICATION SCL TIMING CHARACTERISTICS tHD;STA tLOW tHIGH tRC tFC START condition hold time SCL LOW time SCL HIGH time SCL rise time SCL fall time 14 tCLCL1 16 tCLCL 14 tCLCL 1s1
1
Note 2 Note 2 80 tCLCL Note 5 0.3s6
3
4.0s 4.7s 4.0s 1.0s 0.3s 250ns 0ns 4.7s 4.0s 4.7s 1.0s
0.3s1
SDA TIMING CHARACTERISTICS tSU;DAT1 tHD;DAT tSU;STA tSU;STO tBUF tRD Data set-up time Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time 250ns 0ns 14 tCLCL 14 tCLCL 1s4
1
Note 2 Note 2 Note 2 Note 2 Note 2 Note 5
14 tCLCL1
1
tFD SDA fall time 0.3s4 0.3s 6 0.3s NOTES: 1. At fCLK = 3.5MHz, this evaluates to 14 x 286ns = 4s, i.e., the bit-level I2C interface can respond to the I2C protocol for fCLK 3.5 MHz. 2. This parameter is determined by the user software, it has to comply with the I2C. 3. This value gives the autoclock pulse length which meets the I2C specification for the specified XTAL clock frequency range. Alternatively, the SCL pulse may be timed by software. 4. Spikes on SDA and SCL lines with a duration of less than 4 x fCLK will be filtered out. 5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be 1s. 6. The maximum capacitance on bus lines SDA and SCL is 400pF.
1999 Jul 23
13
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00007
Figure 2. External Data Memory Read Cycle
1999 Jul 23
14
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00069
Figure 3. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 4. Shift Register Mode Timing
1999 Jul 23
15
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
repeated START condition START or repeated START condition tRD STOP condition 0.7 VCC 0.3 VCC tBUF tFD tRC tFC tSU;STO 0.7 VCC 0.3 VCC tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 tSU;STA START condition
SDA (INPUT/OUTPUT)
SCL (INPUT/OUTPUT)
SU00107A
Figure 5. Timing SIO1 (I2C) Interface
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 6. External Clock Drive
VDD-0.5
0.2VDD+0.9 0.2VDD-0.1
VLOAD+0.1V VLOAD VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: AC inputs during testing are driven at VDD -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00167
SU00011
Figure 7. AC Testing Input/Output
Figure 8. Float Waveform
30
MAX ACTIVE MODE
25
20 TYP ACTIVE MODE ICC mA 15
10
5
MAX IDLE MODE TYP IDLE MODE 4 MHz 8 MHz 12 MHz 16 MHz
FREQ AT XTAL1
SU00168
Figure 9. ICC vs. FREQ. Valid only within frequency specifications of the device under test
1999 Jul 23
16
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
VDD IDD VDD VDD P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P1.6 P1.7 VDD RST EA P0 VDD
VDD IDD
VDD
RST
* *
(NC) CLOCK SIGNAL
XTAL2 XTAL1 VSS
P1.6 P1.7
* *
SU00169
SU00170
Figure 10. IDD Test Condition, Active Mode All other pins are disconnected
Figure 11. IDD Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 12. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VDD IDD VDD RST EA P0 VDD
(NC)
XTAL2 XTAL1 VSS
P1.6 P1.7
* *
SU00171
Figure 13. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V NOTE: * Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins does not exceed the IOL1 specifications.
1999 Jul 23
17
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
EPROM CHARACTERISTICS FOR 87C528
The 87C528 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C528 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C528 manufactured by Philips. Table 6 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 14 and 15. Figure 16 shows the circuit configuration for normal program memory verification.
Note that the EA/VPP pin must not be allowed to 90 above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Program Verification If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1, 2 and 3 as shown in Figure 16. The other pins are held at the `Verify Code Data' levels indicated in Table 6. The contents of the address location will be emitted on port 0. External pull ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031 H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 9BH indicates 87C528
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 14. Note that the 87C528 is running with a 4 to 6MHz oscillator The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1, 2 and 3, as shown in Figure 14. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 6 are held at the 'Program Code Data' levels indicated in Table 6. The ALE/PROG is pulsed low 25 times as shown in Figure 15. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 3FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the lock bits, repeat the 25 pulse programming sequence using the `Pgm Lock Bit' levels. After one lock bit is programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed.
Program Lock Bits
The 87C528 has 3 programmable lock bits that will provide different levels of protection for the on-chip code and data (see Table 7). Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to full functionality.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and which satisfies the timing specifications, is suitable.
Table 6. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm lock bit 1 Pgm lock bit 2 Pgm lock bit 3 RST 1 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* 0* 0* EA/VPP 1 VPP 1 VPP VPP VPP VPP P2.7 0 1 0 1 1 1 0 P2.6 0 0 0 0 1 1 1 P3.7 0 1 1 1 1 0 0 P3.6 0 1 1 0 1 0 1
NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75 V 0.25 V. 3. Vcc = 5 V 10% during programming and verification. * ALE/PROG receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for 100 s (10 s) and high for a minimum of 10 s.
1999 Jul 23
18
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
EPROM CHARACTERISTICS FOR 87C524
The 87C524 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C524 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C524 manufactured by Philips. Table 6 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 14 and 15. Figure 16 shows the circuit configuration for normal program memory verification.
in Figure 16. The other pins are held at the `Verify Code Data' levels indicated in Table 6. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Program Lock Bits The 87C524 has 3 programmable lock bits that will provide different levels of protection for the on-chip code and data (see Table 7). Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to full functionality. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 9DH indicates 87C524
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 14. Note that the 87C524 is running with a 4 to 6 MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1, 2 and 3, as shown in Figure 14. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 6 are held at the `Program Code Data' levels indicated in Table 6. The ALE/PROG is pulsed low 25 times as shown in Figure 15. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 3FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the lock bits, repeat the 25 pulse programming sequence using the `Pgm Lock Bit' levels. After one lock bit is programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Program Verification If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1, 2 and 3 as shown
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and which satisfies the timing specifications, is suitable.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000uW/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state.
TMTrademark phrase of Intel Corporation. 1999 Jul 23 19
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Table 7. Program Lock Bits
PROGRAM LOCK BITS1,2 LB1 1 2 3 4 U P P P LB2 U U P P LB3 U U U P PROTECTION DESCRIPTION No Program Lock features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from Internal memory, EA is jumped and latched on Reset, and further programming of the EPROM Is disabled. Same as 2, also verify is disabled. Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the lock bits is not defined.
+5 V VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6 MHz XTAL1 VSS P0 EA/VPP ALE/PROG 87C524/8 PSEN P2.7 P2.6 P2.0-P2.5 P3.4 PGM DATA +12.75 V 25 100 s PULSES TO GROUND 0 1 0 A8-A13 A14
SU00172
Figure 14. Programming Configuration
1 ALE/PROG: 0
25 PULSES
1 ALE/PROG: 0
10s MIN
100s+10
SU00018
Figure 15. PROG Waveform
+5 V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6 MHz XTAL1 VSS P0 EA/VPP ALE/PROG 87C524/8 PSEN P2.7 P2.6 P2.0-P2.5 P3.4 PGM DATA 1 1 0 0 ENABLE 0 A8-A13 A14
SU00173
Figure 16. Program Verification 1999 Jul 23 20
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, Vcc = 5 V10%, VSS = 0 V (See Figure 17) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s PARAMETER MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.5 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00174
NOTE:
* FOR PROGRAMMING VERIFICATION SEE FIGURE 14. FOR VERIFICATION CONDITIONS SEE FIGURE 16.
Figure 17. EPROM Programing and Verification
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jul 23
21
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
1999 Jul 23
22
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1999 Jul 23
23
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
1999 Jul 23
24
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
NOTES
1999 Jul 23
25
Philips Semiconductors
Product specification
80C51 8-bit microcontrollers 16K/32K, 512 OTP, I2C, watchdog timer
87C524/87C528
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 07-99 Document order number: 9397 750 06229
Philips Semiconductors
1999 Jul 23 26
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